Instruction Pipeline

Posted: February 13, 2011 in Embedded System

INSTRUCTION PIPELINE:

An instruction pipeline is a technique used in the design of computers to increase their instruction throughput (the number of instructions that can be executed in a unit of time). The main reason for pipelining instructions is that it allows some operations to be carried out in parallel. We haven’t increased the execution speed at which one instruction is executed, what we have done is increased the throughput by allowing a number of tasks to execute simultaneously. Since computers execute billions of instructions it’s throughput that matters.

These are the steps that need to be carried out when a microprocessor executes an instruction:

  1. Fetch the instruction (instruction fetch phase)
  2. Decode the instruction (decode phase)
  3. Where necessary, fetch the operands (operand fetch phase)
  4. Execute the instruction (execute phase)
  5. Write back the result (write-back phase)

 

  • Now to understand the pipelining process more easily, combine the stages 3 and 4.

  1. The instruction Fetch (IF) stage is responsible for obtaining the requested instruction from memory and is stored it in buffer as temporary storage.
  2. The Instruction Decode (ID) stage is responsible for decoding the instruction and sending out the various control lines to the other parts of the processor.
  3. The Execution (EX) stage is where any calculations are performed. The main component in this stage is the ALU.
  4. The Write Back (WB) stage is responsible for writing the result of a calculation, memory access or input into the register file.

The top gray box is the list of instructions waiting to be executed; the bottom gray box is the list of instructions that have been completed; and the middle white box is the pipeline.

Execution is as follows:

Time Execution
0 Four instructions are awaiting to be executed
1
  • the green instruction is fetched from memory
2
  • the green instruction is decoded
  • the purple instruction is fetched from memory
3
  • the green instruction is executed (actual operation is performed)
  • the purple instruction is decoded
  • the blue instruction is fetched
4
  • the green instruction’s results are written back to the register file or memory
  • the purple instruction is executed
  • the blue instruction is decoded
  • the red instruction is fetched
5
  • the green instruction is completed
  • the purple instruction is written back
  • the blue instruction is executed
  • the red instruction is decoded
6
  • The purple instruction is completed
  • the blue instruction is written back
  • the red instruction is executed
7
  • the blue instruction is completed
  • the red instruction is written back
8
  • the red instruction is completed
9 All instructions are executed

 BUBBLE: Occurred due to delay in instruction fetching. Bubbles are like stalls, in which nothing useful will happen for the fetch, decode, execute and writeback.

In cycle 2, the fetching of the purple instruction is delayed and the decoding stage in cycle 3 now contains a bubble. Everything “behind” the purple instruction is delayed as well but everything “ahead” of the purple instruction continues with execution.

Clearly, when compared to the execution above, the bubble yields a total execution time of 8 clock ticks instead of 7.

Disadvantages:

n  Inability to continuously run the pipeline at full speed because of pipeline hazards which disrupt the smooth execution of the pipeline.

Pipeline Hazards

Pipeline hazards are situations that prevent the next instruction in the instruction stream from executing during its designated clock cycle.

Types of hazards:

  1. Structural hazards
  2. Data hazards
  3. Control hazards

Structural Hazards:  Two instructions need to access the same resource.

Control Hazards: The location of an instruction depends on previous instruction

Data Hazards: An instruction uses the result of the previous instruction.

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